A Framework for the Design of the Heterogeneous Hierarchical Routing Architecture of a Dynamically Reconfigurable Application Specific Media Processor
نویسندگان
چکیده
We have recently proposed a tool set that will aid the design of a dynamically reconfigurable processor through the use of a set of analysis and design tools. As part of the tool set, in this paper we propose a heterogeneous hierarchical routing architecture. Compared to hierarchical and symmetrical FPGA approaches building blocks are of variable size. This results in heterogeneity between groups of building blocks at the same hierarchy level as opposed to classical H-FPGA approach. In this paper we also define the methodology for the design and implementation of the proposed architecture, which involves packing, hierarchy formation, placement, network scheduler tools.
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